
`include "mux1x4_defs.v"

`timescale 1ns / 1ps

module mux1x4(
	i_sel,
	i_clr,
	i_in0,
	i_in1,
	i_in2,
	i_in3,
	o_out
);

parameter DATA_WIDTH	= 12;

input [`MUX1X4_SEL_WIDTH-1:0] i_sel;
input i_clr;

input [DATA_WIDTH-1:0]	i_in0;
input [DATA_WIDTH-1:0]	i_in1;
input [DATA_WIDTH-1:0]	i_in2;
input [DATA_WIDTH-1:0]	i_in3;

output [DATA_WIDTH-1:0]	o_out;
reg [DATA_WIDTH-1:0]	o_out;

always@( i_clr or i_sel or i_in0 or i_in1 or i_in2 or i_in3)
begin
	casex( { i_clr, i_sel } )
		{ 1'b1, `MUX1X4_SEL_xx }: o_out = 0;
		{ 1'b0, `MUX1X4_SEL_I0 }:	o_out = i_in0;
		{ 1'b0, `MUX1X4_SEL_I1 }:	o_out = i_in1;
		{ 1'b0, `MUX1X4_SEL_I2 }:	o_out = i_in2;
		{ 1'b0, `MUX1X4_SEL_I3 }: o_out = i_in3;
	endcase
end

endmodule
